1. The Field of the Invention
The present invention relates generally to processes for planarizing a semiconductor substrate surface. More particularly, the present invention relates to processes for abrasively polishing a semiconductor substrate surface with processing parameters selected to cause the rate of reduction of the semiconductor substrate surface height to adjust downward once the semiconductor substrate surface becomes planarized. The present invention is particularly useful for maximizing planarization efficiency during the planarization of an interlevel dielectric layer on a semiconductor structure during integrated circuit fabrication.
2. The Relevant Technology
Modern integrated circuits are manufactured by an elaborate process in which electronic circuits composed of semiconductor devices are integrally formed on a small semiconductor structure. The conventional semiconductor devices which are formed on the semiconductor structure include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of these semiconductor devices are formed on a single semiconductor structure.
Integrated circuits may be arranged as adjoining dies on a common silicon substrate of the semiconductor structure. Between the dies are located surface level scribe regions where the dies will be cut apart to form discrete integrated circuits. Within the dies, the surface of the semiconductor structure is characterized by raised regions that are caused by the formation of the semiconductor devices. FIG. 1 shows an example of these raised regions, where several such raised regions in the form of arrays 14 are depicted separated by lower regions of lesser height in the form of slots 16 on a silicon substrate 12 of a semiconductor structure 10.
It is conventional in the fabrication of integrated circuits to create the semiconductor devices of semiconductor structure 10 by alternately depositing and patterning layers of conducting and insulating material on the surface of semiconductor structure 10. Frequently, in preparation for the deposition of successive layers, the surface of semiconductor structure 10 is required to be rendered smooth and flat. Thus, in order to prepare the surface of semiconductor structure 10 for a material deposition operation, a planarization process is required to be conducted on the surface of semiconductor structure 10.
Planarization is typically implemented by growing or depositing an interlevel dielectric layer 18 of insulating material such as oxide or nitride on semiconductor structure 10, typically to fill in rough or discontinuous areas such as slots 16. Interlevel dielectric layer 18 is deposited as a substantially conformal film, causing it to have a non-planar surface characterized by raised vertically protruding features 20a of a greater height extending upward above arrays 14 and by open troughs 20b of a lower height located above slots 16. The planarization process is used to reduce the height of vertically protruding features 20a down to a target height that is typically a small distance above the level of the tops of arrays 14 where, ideally, a planarized surface will be formed. The small distance may be quantified as a height range that is greater than the height S set forth in FIG. 1. The term "planarized surface," as used herein, refers to a surface which is flat, smooth, and of a continuous height. An example of a properly planarized interlevel dielectric layer is illustrated in FIG. 2, wherein interlevel dielectric layer 18 has been reduced to planarized oxide regions 22 filling in slots 16 between arrays 14.
One commonly used planarization process is abrasive polishing. Abrasive polishing generally involves pressing a wetted polishing surface against semiconductor structure 10 under controlled pressure and temperature and with a constant relative movement. Several forms of abrasive polishing are used, but one of the most common employs a polishing slurry comprised of tiny abrasive indenter particles. As defined herein, the term indenter particle refers to a particulate material added to a polishing solution to render the polishing solution abrasive to a surface being polished. The particulate additive is typically formed of discrete particles of inorganic material such as silica which have a greater hardness than the surface being polished and are therefore abrasive to the surface being polished. The indenter particles can also be formed of a composition of such materials. The constant movement of the abrasive polishing process is, in one form thereof, an abrasive polishing provided by a rotational polishing system. An example of such a system is found in an apparatus known as the Model 372 Polisher manufactured by IPEC Planar Systems of Phoenix, Ariz.
FIG. 3 shows a representative rotational polishing system 26 having a rotatable polishing platen 28, a wafer polishing head assembly 34, and a polishing slurry supply system 36. Polishing platen 28 is typically covered with an underpad 30 and a polishing pad 32 made of a replaceable, relatively soft material such as polyurethane. Together, polishing platen 28, underpad 30, and polishing pad 32 make up what is known as a "pad-stack."
Wafer polishing head assembly 34 holds semiconductor structure 10 adjacent to polishing pad 32. Wafer polishing head assembly 34 includes a motor (not shown) for rotating the polishing head and semiconductor structure 10. Wafer polishing head assembly 34 further includes a polishing head displacement mechanism (not shown) which moves semiconductor structure 10 back and forth across polishing pad 32, and which is also rotated by a motor. Wafer polishing head assembly 34 applies a controlled downward pressure to semiconductor structure 10 to hold semiconductor structure 10 against polishing pad 32.
A polishing slurry 38 is introduced onto polishing pad 32 by polishing slurry supply system 36 and typically contains abrasive indenter particles therein to assist in the mechanical stripping of interlevel dielectric layer 18. Polishing slurry 38 may also contain a chemical additive that chemically modifies the material of interlevel dielectric layer 18 to allow for more rapid polishing rates. This form of abrasive polishing is known as chemical-mechanical polishing (CMP). Abrasive polishing without the use of a slurry is also used for planarization purposes.
In the rotational polishing system depicted in FIG. 3, the surface of semiconductor structure 10 is bathed in polishing slurry 38 that floats within pores or preformed depressions in polishing pad 32 against which semiconductor structure 10 is pressed, such that the indenter particles are pressed against the surface of semiconductor structure 10 under a downward pressure from polishing pad 32. The lateral motion of polishing pad 32 causes the indenter particles to have a trajectory propelling them across the surface of semiconductor structure 10, resulting in volumetric removal of the material of vertically protruding features 20a of semiconductor structure 10. In chemical-mechanical polishing, the polishing mechanism is a combination of mechanical action and chemical reaction with the material being polished with polishing slurry 38.
A related polishing system for providing constant movement is orbital polishing. Orbital polishing is similar to rotational polishing, but in orbital polishing, wafer polishing head assembly 34 is moved by a polishing head displacement mechanism in an oval pattern over polishing pad 32.
Linear track polishing is a further form of abrasive polishing. One difference between linear track polishing and rotational polishing is that the linear track polishing surface comprises a platen in the form of a continuous drive belt that is similarly porous and on which floats the polishing slurry. The term "polishing surface" as used herein is intended to include linear track polishing platens, as well as orbital polishing system surfaces, and rotating polishing system surfaces such as polishing pad 32.
In the semiconductor industry, abrasive polishing is used for a variety of surface planarization processes in addition to interlevel dielectric layer planarization. There are various types of planarizable surfaces typically located on semiconductor structure 10, including conductive and insulating materials such as oxides, nitrides, polysilicon, single crystalline silicon, amorphous silicon, and mixtures thereof, many of which, in current process flows, must be planarized.
As circuit densities increase, abrasive polishing has become one of the most viable techniques for planarization, particularly for interlevel dielectric layers. Abrasive polishing with a slurry is particularly favored for its high rate of planarization. Because of its significant viability, improvements in abrasive slurry types of planarization processes are increasingly being sought.
FIG. 4 illustrates one drawback of current abrasive slurry planarization processes. This drawback involves an adverse effect hereafter referred to as "local over-polishing" that results when raised regions such as arrays 14 separated by regions of a lesser height such as slots 16 are planarized with abrasive polishing in a slurry. FIG. 4 illustrates an intermediate stage in the planarization process with a dotted line showing the location of an intermediate non-planar surface 40 which occurs at an arbitrary time in a conventional abrasive polishing process. The drawback is shown therein as the occurrence of abraded depressions 40a caused by the indenter particles of polishing slurry 38.
The indenter particles in polishing slurry 38 typically have a trajectory that propels the indenter particles toward the bottoms of troughs 20b. The impact of the indenter particles in the bottoms of troughs 20b causes local over-polishing in the form of depressions 40a to occur. Troughs 20b thus continue to exist even after the surface of interlevel dielectric layer 18 has been polished below the original depth of troughs 20b. Local overpolishing 40a is eventually minimized, but not without removing a substantial amount of otherwise planar material underneath vertically protruding features 20a.
To compensate for the foregoing problem, prior art processes "over-deposit" interlevel dielectric layer 18 in order to fully planarize interlevel dielectric layer 18. That is, the prior art processes deposit interlevel dielectric layer 18 with a greater depth than would otherwise be required if local over-polishing did not occur.
As an illustration, in typical prior art process flows, interlevel dielectric layer 18 is deposited with a depth, shown in FIG. 1 as dimension "D," that is more than twice the step height, shown as dimension "S" of vertically protruding features 20a If it were not for local over-polishing, interlevel dielectric layer 18 could be deposited with a thickness above the tops of arrays 14 corresponding approximately to the target thickness plus that of the step height, denoted by the dimension S, plus any required "post-polishing" thickness. Depositing the greater depth of material consumes process time and resources, increasing the cost of the integrated circuit fabrication process. It also takes longer to planarize the layer of greater depth, further increasing fabrication costs by reducing throughput of the integrated circuit fabrication process. Thermal budget is also increased, as it takes longer to harden the greater thickness of interlevel dielectric layer 18 with an anneal process that is generally conducted in conventional process flows.
A deposition of the material being planarized with additional depth is also generally needed to provide a window of time for stopping the planarization process after the polished surface has become planarized such that the height thereof is not overly reduced.
In view of these and other problems of prior art planarization processes, there is a need in the art for an improved process of planarizing structural layers of a surface with an abrasive slurry which avoids the occurrence of localized over-polishing and reduces the need for over-depositing the layers being planarized.